Many situations arise in which it would be advantageous for semiconductor vendors to provide for complementary semiconductor devices on one substrate or chip. Examples of complementary devices include a plurality of common anode diodes on the same substrate as a group of common cathode diodes; or a vertical NPN transistor adjacent a vertical PNP transistor. In the case of the diodes, one chip replaces two chips, whereas in the case of the transistors, a lower performance lateral PNP transistor could be replaced by a vertical PNP transistor provided along side a vertical NPN transistor.
Although providing a complementary substrate has may advantages, the manufacturing process has many difficulties and involves special fabrication techniques which have prevented wide spread manufacture and use of such devices except in specialized applications.
An ideal complementary semiconductor substrate is shown in prior art FIG. 1 and includes a plurality of regions 10,12 separated by a vertical dielectric region 14. Each dielectrically isolated region includes a lightly doped N region 16 or P region 18. In addition to the likely doped regions, the idealized complementary semiconductor substrate also includes a heavily doped horizontal buried layer 20,22 underlying the lightly doped regions, and a vertical heavily doped sinker diffusion 24,26 by which contact to the buried layer is achieved.
Since most applications for a complementary semiconductor substrate require that the semiconductor devices be matched, the thickness X and Y indicated by arrows 28 and 30 respectively should be as equal as possible.
The fabrication of the ideal complementary semiconductor substrate shown in FIG. 1 is illustrated in FIGS. 2A-2C and begins with a Silicon On Insulator (SOI) wafer 40 comprising a silicon layer 42 approximately two to twenty microns thick on an oxide layer 44, which in turn is disposed on a substrate 46. Silicon layer 42 is then heavily doped N+ or P+, as required, to create buried layers 48 and 50 of the finished substrate.
An epitaxial layer 52, FIG. 2B, is then grown over silicon layer 42. Epitaxial layer 52 is then lightly doped N- and P-, 54 and 56 respectively, by selective diffusion. The diffusion of the N- and P- regions requires long time periods at high temperatures because the diffusion process is driven by differential doping gradients which are weak within the lightly doped layer. As a result of the high temperature long diffusion time period, the heavily doped buried layer 42 will also out-diffuse upwardly into the lightly doped layer 52 thus typically reducing the thickness of the lightly doped layer 52. Although the up-diffusion can usually be compensated for by starting with a thicker epitaxial layer 52, the P+ buried layer 50 will generally up-diffuse faster than the N+ buried region 48 due to the nature of the dopants used for buried layer formation.
After completing the N+ and P+ sinker diffusions 58 and 60, FIG. 2C, the structure is complete. Because of the faster up-diffusion of the P+ buried layer, however, the lightly doped layer thickness X illustrated by arrow 62 will be substantially thicker than the lightly doped layer thickness Y illustrated by arrow 64. The resulting semiconductor devices are thus not the "ideal" matched semiconductor devices as shown in FIG. 1 but rather a compromise structure with a corresponding compromise in device performance. Additionally, this inherent problem is a result of the traditional manufacturing technique that requires that the lightly doped N- and P- diffusions be performed after the heavily doped buried layer diffusions.
One method of eliminating the inherent problem of variations in doped layer thickness within a substrate as discussed above is to utilize wafer bonding technology. Two silicon wafers may be bonded together to produce a silicon substrate with particular characteristics as discussed in related U.S. patent application No. 202,112, now abandoned entitled "Wafer Bonding Using Low Temperature Neutral Alloys" and related U.S. patent application No. 295,045 now U.S. Pat. No. 5,004,705 entitled "Inverted Epitaxial Process", both of which are incorporated herein by reference.
As previously disclosed, this technique begins with a lightly doped silicon wafer 70, FIG. 3 which is similar in resistivity to the epitaxial layer discussed in conjunction with FIGS. 2A-2C. N- and P- diffusions 72,74, respectively, are then performed on the wafer to an appropriate depth. Subsequently, N+ and P+ sinker diffusions 76,78, FIG. 3B are performed into the N- and P- diffusions.
After the high temperature diffusions 72-78 have been performed, the N+ and P+ buried layers 80,82, FIG. 3C are then performed last. Utilizing this method, the N+ and P+ diffusions 80,82 can be both shallow and of equal depth, insuring that the N- and P- regions 72,74 are of equal thickness as required for the complementary substrate.
After performing the buried layer diffusions, wafer 70, FIG. 3D, is bonded along surface 84 to a handle wafer 86 comprised of substrate 88 having an oxidized layer 90. Dielectric isolation regions 92-96, FIG. 3E, are then formed. Utilizing this technique, the final thickness of both the N- and P- regions 72,74 can be identical.
One drawback of this technique is that wafer 70, FIG. 3A, becomes "customized" immediately upon the first doping and diffusion steps 72-74 shown in FIG. 3A. Accordingly, the prior art lacks a method for processing one or more semiconductor wafers to provide a semiconductor substrate that is "generic" or partially processed utilizing more sophisticated semiconductor processing techniques, while allowing the partially processed substrate to be subsequently further processed and finished utilizing conventional semiconductor planar processing techniques, thus insuring that the substrate will provide matched semiconductor elements or devices of equal thickness.